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t2801 preliminary information rev. a9, 11-dec-01 1 (27) dect single-chip transceiver description the t2801 is an rf ic for low-power dect appli- cations. the hp-vfqfp-n48-packaged ic is a complete transceiver including image rejection mixer, if amplifier, fm demodulator, baseband filter, rssi, tx preamplifier, power-ramping generator for power amplifiers, inte- grated synthesizer, fully integrated vco, tx filter and modulation compensation circuit for advanced closed- loop modulation concept. no mechanical tuning is necessary in production. electrostatic sensitive device. observe precautions for handling. features supply-voltage range 3 v to 4.6 v (unregulated) auxiliary-voltage regulator on-chip low current consumption few low cost external components no mechanical tuning required non-blindslot and blindslot operation unlimited multislot operation with advanced closed- loop modulation supports multiple reference clocks (10.368 mhz/ 13.824 mhz/ 20.736 mhz) tx preamplifier with 0 dbm output power at 1.9 ghz and ramp-signal generator for sige power amplifier block diagram tank pc rc gf mcc cp vco f : n f : n ctrl logic pd tx / rx switch ir mixer if amp 1 if amp 2 demod bb filter 3-wire bus demod dac rssi tx driver clock data enable rx_on tx_on pu_rx/tx pu_pll tx_data rssi bb_out cf demod if_tank if_in mixer out rf_in tx_out vs_vco cp ld ref_clk vtune vreg vs_reg reg_ctrl vreg_vco vco reg ramp gen ramp_out ramp_set aux reg pu_vco pu_reg gnd_vco d/a i_cpsw figure 1. block diagram ordering information extended type number package remarks T2801-PLH hp-vfqfp-n48 taped and reeled
t2801 rev. a9, 11-dec-01 preliminary information 2 (27) functional block description name description aux reg auxiliary voltage regulator bbf baseband filter cp charge pump dac d/a converter for demodulator tuning demod demodulator gf gaussian filter for transmit data if amp1 1st intermediate frequency amplifier if amp2 2nd intermediate frequency amplifier ir mixer image rejection mixer mcc modulation compensation circuit name description pc programmable counter pd phase detector ramp gen ramp-signal generator rc reference counter rssi received signal-strength indicator tx driver buffer amplifier for tx_out tx/rx switch switches vco signal to ir mixer resp. tx driver vco voltage-controlled oscillator vco reg voltage regulator for vco pinning clock data enable ref_clk ld pu_reg vs_pll vreg reg_ctrl vs_reg gnd_cp vs_cp ramp_out if_in2 if_in1 vs_if tx_out gnd3 rf_in2 rf_in1 gnd2 if_tank2 if_tank1 rssi 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 t2801 rx_on tx_on mixer_out1 pu_vco tx_data vs_mixer gnd_pll pu_rx/tx pu_pull i_cpsw ramp_set mixer_out2 cp gnd_vco vs_vco gnd1 vtune vreg_vco bb_out dac_dec bb_cf reg_dec demod_tank2 demod_tank1 figure 2. pinning
t2801 preliminary information rev. a9, 11-dec-01 3 (27) pin description pin symbol function configuration 1 clock 3-wire-bus: clock input vs_pll 7 2 data 3-wire-bus: data input clock data enable 123 3 enable 3-wire-bus: enable input enable 1,2,3 5k 5k gnd_pll 43 4 ref_clk reference-frequency input vs_pll 7 ref_clk 4 10k gnd_pll 43 10k 5 ld lock-detect output gnd_pll 43 100 ld 5 6 pu_reg power-up input for aux. voltage regulator pu_reg 6 25k 25k gnd_pll 43
t2801 rev. a9, 11-dec-01 preliminary information 4 (27) pin description (continued) pin symbol function configuration 7 vs_pll pll supply voltage gnd_pll 43 gnd2 28 gnd1 18 gnd3 31 gnd_cp 11 gnd_vco 16 vs_mixer 42 vs_if 33 vs_vco 14 vs_cp 12 vs_reg 10 vs_pll 7 8 vreg aux. voltage-regulator output reg_ctrl 9 vs_reg 10 9 reg_ctrl aux. voltage-regulator control output vreg 8 10 vs_reg aux. voltage-regulator supply voltage gnd_pll 43 11 gnd_cp charge-pump ground vs_cp 12 12 vs_cp charge-pump supply voltage cp 13 13 cp charge-pump output gnd_cp 11
t2801 preliminary information rev. a9, 11-dec-01 5 (27) pin description (continued) pin symbol function configuration 14 vs_vco vco voltage-regulator supply voltage vs_vco 14 vreg vco 15 vreg_vco vco voltage-regulator control output vreg_vco 15 16 gnd_vco vco ground gnd_vco 16 17 vtune vco tuning voltage input vtune 17 gnd_vco 16 vreg_vco 15 18 gnd1 ground gnd_pll 43 gnd2 28 gnd1 18 gnd3 31 gnd_cp 11 gnd_vco 16 vs_mixer 42 vs_if 33 vs_vco 14 vs_cp 12 vs_reg 10 vs_pll 7
t2801 rev. a9, 11-dec-01 preliminary information 6 (27) pin description (continued) pin symbol function configuration 19 demod_tank1 demodulator tank circuit demod_ tank1 19 10k 10k demod_ tank2 20 vs_mixer 42 20 demod_tank2 demodulator tank circuit gnd1 18 21 dac_dec decoupling pin for vco_dac dac_dec 21 10k gnd_vco 16 400 vreg_vco 15 22 reg_dec decoupling pin for vco_reg reg_dec 22 42k 2k vreg_vco 15 gnd_vco 16 23 bb_cf baseband filter corner-frequency control input bb_cf 23 vs_if 33 gnd1 18
t2801 preliminary information rev. a9, 11-dec-01 7 (27) pin description (continued) pin symbol function configuration 24 bb_out baseband filter output vs_if 33 gnd1 18 bb_out 24 25 rssi received signal-strength indicator output vs_if 33 rssi 25 13k gnd2 28 26 if_tank1 if tank circuit if_tank1 26 vs_if 33 if_tank2 27 27 if_tank2 if tank circuit gnd2 28 28 gnd2 ground gnd_pll 43 gnd2 28 gnd1 18 gnd3 31 gnd_cp 11 gnd_vco 16 vs_mixer 42 vs_if 33 vs_vco 14 vs_cp 12 vs_reg 10 vs_pll 7
t2801 rev. a9, 11-dec-01 preliminary information 8 (27) pin description (continued) pin symbol function configuration 29 rf_in1 rf input of image reject mixer rf in1 vs_mixer 42 rf in2 30 rf_in2 rf input of image reject mixer rf _ in1 29 gnd2 28 rf _ in2 30 31 gnd3 ground gnd_pll 43 gnd2 28 gnd1 18 gnd3 31 gnd_cp 11 gnd_vco 16 vs_mixer 42 vs_if 33 vs_vco 14 vs_cp 12 vs_reg 10 vs_pll 7 32 tx_out tx driver amplifier output for pa tx_out 32 gnd3 31
t2801 preliminary information rev. a9, 11-dec-01 9 (27) pin description (continued) pin symbol function configuration 33 vs_if if amplifier supply voltage gnd_pll 43 gnd2 28 gnd1 18 gnd3 31 gnd_cp 11 gnd_vco 16 vs_mixer 42 vs_if 33 vs_vco 14 vs_cp 12 vs_reg 10 vs_pll 7 34 if_in1 if input of if amplifier if in1 if in2 4.3k vs_if 33 35 if_in2 if input of if amplifier if _ in1 34 if _ in2 35 4 . 3k gnd2 28 36 ramp_out ramp-generator output for pa power ramping vs_mixer 42 gnd2 28 ramp_out 36
t2801 rev. a9, 11-dec-01 preliminary information 10 (27) pin description (continued) pin symbol function configuration 37 ramp_set slew-rate setting of ramping signal 56 ramp_set 37 vs_mixer 42 gnd2 25 38 rx_on rx control input vs_if 33 39 tx_on tx control input rx_on tx_on 38, 39 5k 5k gnd1 18 40 mixer_out1 mixer output to saw filter 270 270 mixer_ out2 41 mixer_ out1 40 vs_mixer 42 41 mixer_out2 mixer output to saw filter gnd2 28
t2801 preliminary information rev. a9, 11-dec-01 11 (27) pin description (continued) pin symbol function configuration 42 vs_mixer mixer supply voltage gnd2 28 gnd1 18 gnd3 31 vs_vco 14 vs_cp 12 vs_reg 10 vs_pll 7 43 gnd_pll pll ground gnd_pll 43 31 gnd_cp 11 gnd_vco 16 vs_mixer 42 vs_if 33 44 pu_vco vco power-up input pu_vco 44 5k 5k vs_vco 14 gnd_vco 16 45 pu_rx/tx rx/tx power-up input pu_rx/tx 45 25k 25k gnd1 18
t2801 rev. a9, 11-dec-01 preliminary information 12 (27) pin description (continued) pin symbol function configuration 46 pu_pll pll power-up input pu_ pll 46 25k 25k 10k 10k 140k gnd_ pll 43 10k 20k 47 tx_data tx data input of gaussian filter and modulation-compensation circuit tx_data 47 5k 5k vs_pll 7 gnd_pll 43 48 i_cpsw charge pump switch input controls charge pump current i_cpsw 48 5k vs_pll 7 gnd_pll 43
t2801 preliminary information rev. a9, 11-dec-01 13 (27) functional description receiver the rf signal at rf_in is fed to an image rejection mixer ir_mixer with its differential outputs mixer_out1 and mixer_out2 driving an if-saw filter at 110.592 mhz or 112.32 mhz. the if amplifiers if_amp1 and if_amp2 with an external if_tank and an integrated rssi function feed the signal to the demodulator demod working at f = f if /2 ( 55 mhz) and finally to an integrated baseband filter bb. for demodulator tuning in production an integrated 5-bit dig- ital-to-analog (d/a) converter is provided to control the on-chip varicap diode. transmitter the transmit data at tx_data is filtered by an integrated gaussian filter gf and fed to the fully integrated vco operating at twice the output frequency. after modulation the signal is frequency-divided by 2 and fed via a tx/rx switch to the tx_driver. this bus-controlled driver amplifier supplies typical +3 dbm output power at tx_out. a ramp-signal generator ramp_gen, pro- vides a ramp signal at ramp_out for the external power amplifier, is integrated. the slope of the ramp signal is controlled by a capacitor at the ramp_set pin. synthesizer the ir_mixer, the tx_driver and the programmable counter pc are driven by the fully integrated vco (including on-chip inductors and varactors). an 3-bit digital-to-analog converter is used to pretune the frequency. the output signal is frequency- divided to supply the desired frequency to the tx_driver, 0/90 degree phase shifter for the ir_mixer and to be used by the pc for the phase detec- tor pd (f pd = 3.456 mhz). unlimited multislot operation is possible by using the integrated advanced closed-loop modulation concept based on the modulation compensation circuit mcc. power supply an integrated bandgap-stabilized voltage regulator for use with an external low-cost pnp transistor is imple- mented. multiple power-down and current saving modes are provided.
t2801 rev. a9, 11-dec-01 preliminary information 14 (27) pll principle rf_in programable counter pc o main counter mc o swallow counter sc f vco = f pd x (s mc x 32 + s sc ) f vco phase frequency divider by 2 pa driver detector pd vco mixer vco dac f pd = 3.456 mhz gf_data controlled phase shifting modulation gaussian compensation mcc filter gf reference counter rc 6.912 mhz ref_clk s rc 13.824mhz 4 20.736mhz 6 1.152 mbit/s pll reference tx_data frequency ref_clk baseband controller 3 10.368mhz ext. loop filter charge pump figure 3.
t2801 preliminary information rev. a9, 11-dec-01 15 (27) the following table shows the lo frequencies for rx and tx for the dect band plus additional channels for the extended dect band. intermediate frequencies of 110.592 mhz and 112.32 mhz are supported. table 1 lo frequencies mode f if /mhz channel f ant /mhz f vco /mhz s mc s sc tx c9 1881.792 1881.792 34 1 c8 1883.520 1883.520 34 2 ... ... ... ... ... c1 1895.616 1895.616 34 9 c0 1897.344 1897.344 34 10 c10 1899.072 1899.072 34 11 c11 1900.800 1900.800 34 12 ... ... ... ... ... c29 1931.904 1931.904 34 30 c30 1933.632 1933.632 34 31 rx 110.592 c9 1881.792 1771.200 32 1 c8 1883.520 1772.928 32 2 ... ... ... ... ... c1 1895.616 1785.024 32 9 c0 1897.344 1786.752 32 10 c10 1899.072 1788.480 32 11 c11 1900.800 1790.208 32 12 ... ... ... ... ... c29 1931.904 1821.312 32 30 c30 1933.632 1823.040 32 31 rx 112.320 c9 1881.792 1769.472 32 0 c8 1883.520 1771.200 32 1 ... ... ... ... ... c1 1895.616 1783.296 32 8 c0 1897.344 1785.024 32 9 c10 1899.072 1786.752 32 10 c11 1900.800 1788.480 32 11 ... ... ... ... ... c29 1931.904 1819.584 32 29 c30 1933.632 1821.312 32 30 formula tx: f ant = f vco = 1.728 mhz (32 s mc + s sc ) rx: f ant = 1.728 mhz (32 s mc + s sc ) + f if
t2801 rev. a9, 11-dec-01 preliminary information 16 (27) control signals table 2 signal function i_cpsw controls the charge pump current pu_reg activates aux voltage regulator supplying the complete transceiver. pu_vco activates vco voltage regulator which supplies only the vco. pu_rx/tx activates rx/tx switch. pu_pll activates pll circuits: pc, pd, cp, rc rx_on activates rx circuits: bbf, demod, if amp, ir mixer tx_on activates tx circuits: tx-driver, ramp gen. starts ramp signal at ramp out. data word 1 bit d10 activates gf in tx mode. data word 1 bit d9 activates mcc in tx mode. table 3 mode tx mode rx mode rssi only pu_reg 1 1 1 pu_vco 1 1 1 pu_rx/tx 1 1 1 pu_pll 1 1 1 rx_on 0 1 1 tx_on 1 0 1 bb filter off on off demodulator off on off if amplifiers and rssi off on on ir mixer off on on rx switch off on on tx switch on off off tx driver on off off ramp generator on off off programmable counter on on on voltage-controlled oscillator on on on gaussian filter on off off phase detector / charge pump on on on modulation compensation circuit on off off reference counter on on on typ. current consumption / ma @ v s = 3.2 v 54 85 80
t2801 preliminary information rev. a9, 11-dec-01 17 (27) serial programming bus the transceiver is programmed by the 3-wire bus (clock, data and enable). after setting enable signal to low condition, on the rising edge of the clock signal, the data is transferred bit by bit into the shift register, starting with the msb-bit. after enable returning to high condition the programmed information is loaded into the addressed latches, according to the addressbit condition (last bit). additional leading bits are ignored and there is no check made how many pulses arrived during enable-low condition. during enable low condition the bus current is increased to speed up the bus logic. the programming of the transceiver is separated into two data words. data word 1 controls mainly the channel in- formation together with settings, which are closely related with the channel. dataword 2 holds setup informa- tion, which is adjusted during production. data word 1 msb lsb data bits address bit d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a0 rc sc mc vcos 1 1 gf mcc gfcs vcodac cpcs 1 data word 2 e10 e9 e8 e7 e6 e5 e4 e3 e2 e1 e0 a0 demoddac mccs test 0 data word 1 programs pll settings with the reference counter bits d21 d22 rc (reference counter) d22 d21 s rc ref_clk 0 0 3 10.368 mhz 0 1 4 13.824 mhz 1 0 6 20.736 mhz with the main counter bits d14 d15 mc (main counter) d15 d14 s mc 0 0 32 0 1 33 1 0 34 1 1 35 with the swallow counter bits d16 d20 sc (swallow counter) d20 d19 d18 d17 d16 s sc 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 2 ... ... 1 1 1 0 1 29 1 1 1 1 0 30 1 1 1 1 1 31
t2801 rev. a9, 11-dec-01 preliminary information 18 (27) vco select (rx/tx vco) with bit d13 used to switch between rx/tx vco d13 vcos (vco select) 0 rx-vco 1 tx-vco gaussian filter on/off with bit d10 gf is used only in tx mode d10 gf (gaussian filter) 0 off 1 on modulation compensation circuit on/off with bit d9 mcc is used only in tx mode d9 mcc (modulation compensation circuit) 0 off 1 on gfcs adjustment with bit d6 d8 only in tx mode ef fective for setting the frequency devi- ation of the modulation gfcs (gaussian filter settings) d8 d7 d6 gfcs 0 0 0 60% 0 0 1 70% 0 1 0 80% 0 1 1 90% 1 0 0 100% 1 0 1 110% 1 1 0 120% 1 1 1 130% vco_dac adjustment with bit d3 d5 used to pretune the vco frequency in case of production tolerances of the device. tuning voltage in locked condi- tion should be around 1.8 v at room temperature. this gives margin for ambient temperature changes. pretune dac voltage d5 d4 d3 f vco /% 0 0 0 5 0 0 1 ... 0 1 0 ... 0 1 1 ... 1 0 0 ... 1 0 1 ... 1 1 0 ... 1 1 1 5 cpcs adjustment with bit d0 d2 used to adjust the charge pump current. this can be used to compensate the change of the tuning sensitivity over frequency and device tolerances. cpcs (charge-pump current settings) d2 d1 d0 cpcs 0 0 0 4 0 0 1 3 0 1 0 2 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 2 1 1 1 3
t2801 preliminary information rev. a9, 11-dec-01 19 (27) data word 2 programs demoddac adjustment with bits e6 e10 only in rx mode ef fective. used to tune the demodulator center frequency and allows to compensate tolerances of external components and the t2801. demod dac voltage e10 e9 e8 e7 e6 f ifcenter % 0 0 0 0 0 5 0 0 0 0 1 ... 0 0 0 1 0 ... ... 1 1 1 0 1 ... 1 1 1 1 0 ... 1 1 1 1 1 5 mccs adjustment with bits e3 e5 only in tx mode ef fective. adjusts the modulation com- pensation circuit for closed loop modulation. this adjustment is done with a test sequence of a long stream of ,1` ,0`. the correct setting is achieved, if the modula- tion is not affected by the pll. mccs (modulation compensation settings) e5 e4 e3 mccs 0 0 0 60% 0 0 1 70% 0 1 0 80% 0 1 1 90% 1 0 0 100% 1 0 1 110% 1 1 0 120% 1 1 1 130% test mode settings with bit e0 e2 and d11 in normal operation lock detect output is used. all other settings are for test only. d11 e2 e1 e0 signal at lock detect output cp mode 1 0 0 0 lock detect active 0 0 0 1 rc out active 1 0 1 0 pc out active x 0 1 1 mcctest: rc out divided by 2048 active 1 1 0 0 lock detect high imp. 0 1 0 1 rc out high imp. 1 1 1 0 pc out high imp. x 1 1 1 gftest: rc out divided by 2 high imp.
t2801 rev. a9, 11-dec-01 preliminary information 20 (27) 3-wire bus protocol timing diagram data clock enable tt tec ts tc th tl tper 16525 figure 4. description symbol min. value unit clock period tper 125 ns set time data to clock ts 60 ns hold time data to clock th 60 ns clock pulse width tc 60 ns set time enable to clock tl 200 ns hold time enable to data tec 0 ns time between two protocols tt 250 ns tx data timing refclk tx_data t s t h set-up time tx data ts 10 ns hold time tx data th 10 ns figure 5. tx data timing ts and th must be considered for both (falling and rising) edges of refclk when using ref_clk = 10.368 mhz. absolute maximum ratings all voltages refer to gnd parameter symbol min. max. unit supply voltage regulator pin 10 v s_reg 3.2 4.7 v supply voltage pins 7, 12, 14, 33 and 42 v s 3.0 4.7 v logic input voltage pins 1, 2, 3, 38, 39, 44, 45, 46, 47 and 48 v in 0.3 v s v junction temperature t jmax 150 c storage temperature t stg 40 150 c thermal resistance parameter symbol value unit junction ambient r thja t.b.d. k/w
t2801 preliminary information rev. a9, 11-dec-01 21 (27) operating range parameter symbol min. typ. max. unit supply voltage regulator pins 10 v s_reg 3.2 3.6 4.6 v supply voltage pins 7, 12, 14, 33 and 42 v s 3.0 3.0 4.6 v ambient temperature t amb 25 +85 c electrical characteristics test conditions (unless otherwise specified): v s_reg = 3.2 v, t amb = 25 c parameter test conditions / pins symbol min. typ. max. unit ir mixer pins 29, 30, 40 and 41 input impedance pins 29 and 30 z in 50 w input matching pins 29 and 30 vswr in <2:1 image rejection ratio pins 40 and 41 irr 20 db dsb noise figure pins 40 and 41 nfdsb= nfssb 10 db conversion gain r load = 200 w g conv 11 db input interception point pins 40 and 41 iip3 10 dbm if amplifier pins 26, 27, 34 and 35 input impedance pins 34 and 35 z in 200 400 w lower cut-off frequency fl 3db 90 mhz upper cut-off frequency fu 3db 130 mhz power gain gp 85 db bandwidth of external tank circuit pins 26 and 27 bw3db 10 mhz noise figure nf 9 db rssi pins 25, 34 and 35 rssi sensitivity at if_in1, if_in2 pins 34 and 35 p min 20 db m v rssi compression at if_in1, if_in2 pins 34 and 35 p max 100 db m v rssi dynamic range dr 80 db rssi resolution slope of the rssi has to be steady acc 2 db rssi rise time p in = 30 to 100 db m v, pin 25 t r 1 m s rssi fall time p in = 100 to 30 db m v, pin 25 t f 1 m s quiescent output current @ p in < 20 db m v at if_in1, if_in2 pin 25 i out 30 m a maximum output current @ p in = 100 db m v at if_in1, if_in2 pin 25 i out 150 m a
t2801 rev. a9, 11-dec-01 preliminary information 22 (27) electrical characteristics (continued) test conditions (unless otherwise specified): v s_reg = 3.2 v, t amb = 25 c unit max. typ. min. symbol test conditions / pins parameter fm demodulator, bb-filter pins 19, 20, 23 and 24 co-channel rejection ratio @ p in = 75 dbm at ir-mixer input ccrr 10 db sensitivity quality factor of external tank circuit approx. 20, f res = f if /2, pin 24 s 0.5 v/mhz amplitude of recovered signal nominal deviation of signal 288 khz, pin 24 a 450 mvss corner frequency pin 23: c = 68 pf f c 680 khz output voltage dc range pin 24 v outdc 1 vs1 v dac for fm demodulator (internally connected) demod_dac range (see bus protocol e6 ... e10) f ifcenter 5 % vco rxvco frequency range vcos = `0' bit d13 f vco 1750 1840 mhz txvco frequency range vcos = `1' bit d13 f vco 1860 1950 mhz tuning gain g tune 40 mhz/v frequency control voltage range pin 17 v tune 0.4 2.8 v vco_dac range (see bus protocol d3 ... d5) d f vco,dac 5 % pll scaling factor prescaler s psc 32 / 33 scaling factor main counter s mc 32 / 33 / 34 / 35 scaling factor swallow counter s sc 0 31 external reference input frequency ac coupled sinewave pin 4 f ref_clk 10.368 13.824 20.736 mhz mhz mhz external reference input voltage ac coupled sinewave pin 4 v ref_clk 50 250 mv rms scaling factor reference counter s rc 3 / 4 / 6 / 8 charge pump pin 13 output current v cp = v vs_cp / 2, i_cpsw = `1' pin 48 i cp_nom 6.5 ma output current v cp = v vs_cp / 2, i_cpsw = `0' pin 48 i cp_nom 1.2 ma current scaling i cp = i cp_nom + cpcs * i cp_step (see bus protocol d0 ... d2) i cp_step 0.2 ma leakage current i l 100 pa
t2801 preliminary information rev. a9, 11-dec-01 23 (27) electrical characteristics (continued) test conditions (unless otherwise specified): v s_reg = 3.2 v, t amb = 25 c unit max. typ. min. symbol test conditions / pins parameter gaussian transmit filter (gaussian shape b * t = 0.5) tx data filter clock 12 taps in filter f txfclk 13.824 mhz frequency deviation gf fm_nom 350 khz frequency deviation scaling gf fm = gf fm_nom * gfcs (see bus protocol d6 ... d8) gfcs 60 130 % modulation compensation circuit oversampling ovs 6 digital sum variation dsv 85 current scaling factor (see bus protocol e3 ... e5) mccs 60 130 % vco switch and tx driver pin 32 power gain @ p in = 40 dbm gp 30 db output impedance pin 32 z out 100 w maximum output power pin 32 p max 0 3 dbm gain compression @ tx_rf_out, pin 32 p 1db 1 dbm output interception point pin 32 oip3 10 dbm ramp generator pins 36 and 37 minimum output voltage according to ramp_set input v min 0.2 v maximum output voltage according to ramp_set input v max 1.95 v rise time c ramp = 270 pf at pin 37 t r 5 m s fall time c ramp = 270 pf at pin 37 t f 5 m s lock detect and test mode output pin 5 lock detect output, test mode output locked = `1', unlocked = `0' test modes (see bus protocol e0 ... e2) ld leakage current v oh = 4.6 v i l 5 m a saturation voltage i ol = 0.5 ma v sl 0.4 v auxiliary regulator pins 8, 9 and 10 output voltage v sreg = 3 v pin 8 v reg 2.9 3.0 3.1 v supply voltage rejection v pin10 = v dc + 0.1 v pp f pin10 = 0.1 to 10 khz c pin8 = 100 nf svr t.b.d. db vco regulator pins 14, 15 and 12 output voltage v svco = 3 v pin 15 v reg_vco 2.6 2.7 2.8 v 3-wire bus clock f clock 6.912 mhz
t2801 rev. a9, 11-dec-01 preliminary information 24 (27) electrical characteristics (continued) test conditions (unless otherwise specified): v s_reg = 3.2 v, t amb = 25 c unit max. typ. min. symbol test conditions / pins parameter logic input levels (clock, data, enable, rx_on, tx_on, pu_vco, tx_data, i_cpsw) pins 1, 2, 3, 38, 39, 44, 47 and 48 high input level = `1' v ih 1.5 v low input level = `0' v il 0.5 v high input current = `1' i ih 5 5 m a low input current = `0' i il 5 5 m a standby control pins 6, 45 and 46 power up pu_reg = `1` pu_rx/tx = `1` pu_pll = `1` high input level pin 6 pin 45 pin 46 v pu_reg v pu_rx/tx v pu_pll 2.0 v standby pu_reg = `0` pu_rx/tx = `0` pu_pll = `0` low input level pin 6 pin 45 pin 46 v pu_reg,off v pu_rx/tx,off v pu_pll,off 0.7 v power up pu_reg = `1` pu_rx/tx = `1` pu_pll = `1` high input current v pu = 3 v pin 6 v pu = 5.5 v pin 45 v pu = 3 v pin 46 v pu = 5.5 v i pu_reg i pu_rx/tx i pu_pll 20 60 100 200 30 80 125 300 40 100 150 400 m a m a m a m a standby pu_xxxx = `0' low input current v pu = 0 v pin 6, v pu = 0.5 v pins 45, 46 i pu,off 0.1 1 m a m a settling time v s = 0 active operation switched from v s = 0 to v s = 3v t soa < 10 m s settling time standby active operation switched from pu = `0' to pu = `1' t ssa < 10 m s settling time active operation standby switched from pu = `1' to standby t sas < 2 m s power supply pins 7, 10, 12, 14, 33 and 42 total supply current rx i s 85 ma pp y rssi only i s 82 ma tx i s 54 ma tx (mcc, gf active) i s 58 ma standby current pu_rx/tx = gnd i s 1 10 m a supply current cp v vs_cp = 3 v, pll in lock condition pin 13 i cp 1 m a
t2801 preliminary information rev. a9, 11-dec-01 25 (27) application circuit vcc bb_out rssi 48 i_cpsw 47 tx_data 46 pu_pll 45 pu_rx/tx 44 pu_vco 43 gnd_pll 42 vs_mixer 41 mixer_out2 40 mixer_out1 39 tx_on 38 rx_on 37 ramp_set cp 13 vs_vco 14 vreg_vco 15 gnd_vco 16 vtune 17 gnd1 18 demod_tank1 19 demod_tank2 20 dac_dec 21 reg_dec 22 bb_cf 23 bb_out 24 12 vs_cp 11 gnd_cp 10 vs_reg 9 reg_ctrl 8 vreg 7 vs_pll 6 pu_reg 5 ld 4 ref_clock 3 enable 2 data 1 clock rssi 25 if_tank1 26 if_tank2 27 gnd2 28 rf_in1 29 rf_in2 30 gnd3 31 tx_out 32 vs_if 33 if_in1 34 if_in2 35 ramp_out 36 pu_vco pu_rx/tx pu_pll tx_data i_cpsw tx_on rx_on ld pu_reg clock data enable ref_clk bc808 or similar 560 pf 220 pf 15 pf 15 pf 270 nh 33 pf 33 pf 180 nh 56 pf 470 nf 180 w 150 nf 22 nf 68 pf 2.2 nf 100 pf tbd tbd 18 pf 100 nh tx_out rf_in saw filter tfs 112b tantal tantal 4.7 nf ramp_out 68 pf t2801 figure 6. application circuit
t2801 rev. a9, 11-dec-01 preliminary information 26 (27) package information
t2801 preliminary information rev. a9, 11-dec-01 27 (27) ozone depleting substances policy statement it is the policy of atmel germany gmbh to 1. meet all present and future national and international statutory requirements. 2. regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. it is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (odss). the montreal protocol ( 1987) and its london amendments ( 1990) intend to severely restrict the use of odss and forbid their use within the next ten years. various national and international initiatives are pressing for an earlier ban on these substances. atmel germany gmbh has been able to use its policy of continuous improvements to eliminate the use of odss listed in the following documents. 1. annex a, b and list of transitional substances of the montreal protocol and the london amendments respectively 2. class i and ii ozone depleting substances in the clean air act amendments of 1990 by the environmental protection agency (epa) in the usa 3. council decision 88/540/eec and 91/690/eec annex a, b and c (transitional substances) respectively. atmel germany gmbh can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. 8. we reserve the right to make changes to improve technical design and may do so without further notice . parameters can vary in different applications. all operating parameters must be validated for each customer application by the customer. should the buyer use atmel products for any unintended or unauthorized application, the buyer shall indemnify atmel against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. data sheets can also be retrieved from the internet: http://www.atmelwm.com atmel germany gmbh, p.o.b. 3535, d-74025 heilbronn, germany telephone: 49 (0)7131 67 2594, fax number: 49 (0)7131 67 2423

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